The focus of this year's annual symposium is "Functional Stacks for Logic and Memory Devices." The exploration of functional stacks for future (sub-15 nm node) devices will include high-k/metal gate stacks for Si, Ge, III-V high performance MOSFETs; metal/high-k/metal gate stacks for high-k/metal gate for flash memory metals and magnetic material needed for spin-based devices. Sessions on future devices such as fully depleted, non-planar and tunneling transistors will be included. A special session on interface defects in III-V will be included.
The symposium will feature industry experts presenting their latest research in both keynote and invited talks. Experts from industry, consortia and universities will be present.
Gold Standard Simulations Ltd. is having a course on statistical nano-CMOS variability and reliability by Professor Asen Asenov at The Sagamore prior to the Advanced Gate Stack Symposium, October 17-18, 2011. Click here for more information.
