| SystemVerilog User Group Agenda
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9:00 - 9:30
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SystemVerilog User Group arrival and check-in |
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9:30 - 9:45
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Welcome and Introduction by Dennis Brophy of Accellera |
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9:45 - 10:45
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SystemVerilog Design Fundamentals by Cliff Cummings of Sunburst Design
This tutorial introduces engineers to new IEEE 1800-2005 SystemVerilog RTL and Behavioral Design enhancements to increase design & coding efficiency. This seminar will not provide a history of, or justification for the SystemVerilog language. It is assumed that engineers who attend already understand the importance of SystemVerilog and are interested in a quick introduction to its syntax and capabilities. |
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10:45 - 11:00
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Break |
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11:00 - 12:00
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SystemVerilog Assertion Tricks for Designers by Cliff Cummings of Sunburst Design
The introduction of SystemVerilog Assertions (SVA) added the ability to perform concurrent assertions for both design and verification, but some engineers have complained about SVA verbocity or do not understand some of the better methodologies to take full advantage of SVA.This presentation shows valuable SystemVerilog Assertion tricks for designers, including the use of long SVA labels and concise SVA coding styles from Cliff's award-winning SNUG-San Jose 2009 paper. The concise SVA coding styles detailed in this presentation can reduce concurrent SVA coding efforts by 50%-80% over conventional SVA coding techniques.
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12:00 - 1:00
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Lunch |
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1:00 - 1:30
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VIP Interoperability Standards Update by Dennis Brophy of Accellera
Accellera recently approved version 1.0 of its Verification Intellectual Property (VIP) Recommended Practices guideline. The guideline was created to address a significant industry need to make VIP interoperate between different verification methodologies. . Typically, legacy code is written in one methodology and companies either want to migrate to the other or they need to use existing VIP from the other library. The integration at times can be straight forward, like attaching a protocol monitor, but often the work is extensive and requires a significant amount of knowledge about both methodologies to make them interoperate correctly. The Accellera guideline offers a solution to the VIP interoperability issue. It starts out by stepping the user through a high-level overview, which is intended to quickly redirect the user to the practice(s) that address their specific circumstances. An examination of how to use VIP written for VMM or OVM in the other's environment will be detailed. In the process information about where to find the open-source methodology interoperability kit will be shared and an explanation on how to use it will be included. |
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1:30 - 2:30
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OVM: The Methodology Platform by Allan Crone of Mentor Graphics
The true measure of a verification methodology is what you can do with it, not just what’s in it. This session will provide an overview of the Open Verification Methodology and show how it provides a true platform to simplify and strengthen your functional verification efforts. Architected to maximize reuse and streamline the creation of verification IP components, the OVM lets you seamlessly take advantage of advanced verification technologies, from verification planning, and stimulus generation to coverage closure, emulation and HW/SW verification – all within the context of OVM. The session will also include a discussion of new OVM features including the OVM register package, the OVM Low-Power methodology and the recently-approved VIP Interoperability library from Accellera which allows you to include legacy VMM IP in your OVM environment. |
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2:30 - 2:45
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Break |
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2:45 - 3:30
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Verification with SystemVerilog by Srinivasan Venkataramanan of CVC Pvt. Ltd
Achieving higher quality design through SystemVerilog & Questa The design and verification of a complex image processing system consisting of various image enhancement techniques is a very challenging and daunting task. The sheer complexity of algorithms and their wide range of applications mean that there are many different scenarios and corner cases to verify and also to ensure that the system is behaving correctly.
Traditionally such designs have been verified with mostly directed tests and teams have been successful in doing so. However, with more complex systems being designed with shrinking time-to-market, this approach doesn't scale up. The complexity factor requires more powerful verification technologies while the time-to-market pressure involves managing and mitigating risks.
Recent advances in Higher Level Verification techniques aim to address these challenges. However a raw set of features such as constraints, coverage, assertions etc. alone don't appeal directly to such design teams as they are left to ponder which one to use where. This is where a tailored verification approach based on proven and robust verification platform fits in.
In this presentation we share our recent experience of verifying an image correction algorithm block using sophisticated verification techniques offered by SystemVerilog along with robust and easy-to-use verification platform - Questa.
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3:30 - 4:15
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SystemVerilog-Experience on building OVM-based VIPs by Ashish Deokule of eInfochips
System Verilog is a new modeling language based on HDL and HVL, which is intended to enable System level design , Verification and IP exchange. Much has been talked about System Verilog, and people started finding System Verilog as a good language for Architecture Exploration, Design, Verification, Transaction Layer Modelling etc. HVL- Veterans may feel that System Verilog is not flexible as today’s much flexible languages like “e” language from Cadence, Synopsys’ “Vera” etc. This article gives a real life experience and introduction to “Verification IP using System Verilog”. It also gives in depth overview of how Engineers can use Verification methodologies like functional coverage, random generation, Assertions etc using System Verilog. Optimal System Level Verification solution is becoming paramount key to employ a proper verification methodology. System Verilog can be very effective solution as a single language for Design and Verification, and still ensuring “All effective methodologies” in today’s multi-language, methodology-centric ASIC cycle.
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4:15 - 5:00
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OVM Framework Generator by Vasantha Kumar and Lakshman Easwaran of Mindtree
A lot of time and effort is invested in creating a new verification environment for an IP. Considerations like re-usability, flexibility, scalability and less time to verify its functionality makes it even more challenging for any verification engineer.
Methodology driven verification addresses the above mentioned challenges effectively. System Verilog OVM is one such methodology which provides a platform to build a robust verification environment, which takes care of all the verification challenges.
It is observed that coding style of basic structure of most of the OVM components is common as per OVM Guidelines. About 20-30% of the total verification time is spent in creating the basic OVM structure. This affects IPs which needs to be verified thoroughly in a short span of time, and the pressure builds up enormously towards the end.
In this paper a user-friendly productivity tool is presented. This tool automates the complete flow, right from the creation of the Directory structure, customization & building of the OVM components, automatic creation and integration of standard & proprietary Protocol Checkers, creation of Bus Functional Models & Scoreboard for standard interfaces, building the necessary Scripts and integrating all the created files to deliver a Compile Clean OVM environment. The user intervention is required only to add the necessary logic in the components generated. This tool enables engineers across projects to verify the IPs in a minimal span of time and increases the productivity by 30-40%. |
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5:00 - 5:15
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Drawing for 5 OVM Cookbooks (must be present to win)
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5:15 - 6:15
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Reception & Networking
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